1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits, and particularly to a semiconductor integrated circuits which has a plurality of circuits that operate in synchronism with a timing signal in parallel formation and the number of circuits operating in parallel is changed in accordance with an operation mode. More particularly, the present invention is concerned with a semiconductor device which operates in synchronism with an external clock signal and handles input or output data having a variable data length, such as a synchronous dynamic random access memory (SDRAM).
2. The Description of the Related Art
A semiconductor device is designed to form, on a chip, a circuit arrangement which makes it possible to implement a plurality of functions, which can selectively be operated by a mode instruction signal from the outside of the device or by changing interconnections in order to reduce the production cost and quickly meet requirements in the markets. For example, there has been considerable activity in increasing the integration density of a semiconductor memory device such as a DRAM. However, the conventional one-bit data width does not efficiently use an increased memory capacity per chip. Hence, the data width is generally designed to have a multiple-bit arrangement. Nowadays, DRAMs are available which have various data widths (bit widths) such as a 1-bit data width, a 4-bit data width, an 8-bit data width and a 16-bit data width. Generally, a given part such as a memory cell array is commonly used to the DRAMs having the different data widths, and an input/output part is selectively driven in accordance with the data width to be used. Hence, the different types of memory devices having the different data widths can be produced from one chip. A multiple-bit-data-width memory device is equipped with an internal circuit capable of setting the data width to be used and is then shipped.
Another multiple-bit-data-width memory device is equipped with an internal circuit capable of, during operation, arbitrarily setting the desired data width in response to an external mode instruction signal.
The bit-multiplication of the data width requires an arrangement in which a plurality of memory cells can be accessed by the same address in accordance with the data width. For example, a first arrangement activates a plurality of column lines and/or a plurality of word lines in response to a single address. A second arrangement groups a plurality of memory cells into a plurality of blocks (banks), which can be simultaneously accessed. A combination of the first and second arrangements can be used.
A change of the data width requires that a part of write (input) data is inhibited from being written into memory cells in the data write operation and a part of read (output) data is inhibited from be read from memory cells and output to data output terminals in the data read operation. The above inhibiting process is referred to as a mask process. In the mask process performed in the data write operation, data to be masked is prevented from being written into memory cells, and associated word lines and/or column lines are not activated. Hence, the mask process for write data is performed in an address decoder or a circuit around the address decoder. In a case whether the mask process is performed on the block basis, an access to a block to be masked is stopped.
In contrast, a particular problem does not occur in the data read operation even when the memory cells are normally accessed. Hence, it is enough to stop some data output circuits from outputting data. Even in the case where the mask process is performed on the block basis, it is required to stop the data output circuits of the blocks to be masked outputting data.
FIG. 1 is a block diagram of a conventional DRAM having the function of masking output data, and a structure of a data output circuit is illustrated in detail. The DRAM device illustrated shown in FIG. 1 is an SDRAM device in which the data input/output operation and internal operations are performed in synchronism with a clock signal externally applied thereto in order to operate the DRAM device at a high speed. An intermediate operation is a pipeline operation of a plurality of stages.
The SDRAM device shown in FIG. 1 includes a plurality of blocks 8-0-8-n, each of which blocks includes a memory cell array 1, a sense amplifier 17 and a data amplifier 18. Although not illustrated, each of the blocks further includes the same circuits as those of the conventional DRAM device, that is, an address decoder (which includes a row decoder and a column decoder), a driver and a write amplifier. Data output circuits 20-0-20-n are respectively provided to the blocks 8-0-8-n.
At the time of reading data, a memory cell of the memory cell array 1 specified by an address signal is accessed and data stored in the specified memory cell is amplified. Further, the data is amplified by a data amplifier 18, which outputs complimentary data signals to the output circuit 20-0. The complementary data signals are input to transfer gates 44 and 45 via inverters 41 and 42, respectively. The transfer gates 44 and 45 are open while an output timing signal clko is at a high level, and respectively transfer the output signals of the inverters 41 and 42 to a flip-flop made up of inverters 46 and 47 and a flip-flop made up of inverters 48 and 49. The output signals of the inverters 41 and 42 have been settled when the transfer gates 44 and 45 are opened, and are thus transferred to the two flip-flops when the transfer gates 44 and 45 are opened. The output signals of the two flip-flops are applied to gates of output transistors 50 and 51, which are switched to respective states corresponding to the output signals of the flip-flops. If the transistor 50, which is a p-channel transistor, is turned on, the transistor 51, which is an n-channel transistor, is turned off, so that a high-level data signal is output to an output terminal 53-0. The same operation as described above is performed in each of the other output circuits 20-1-20-n.
The transfer gates 44 and 45 are in the closed state while the output timing signal clko is at a low level, and maintain states obtained when the transfer gates 44 and 45 are closed until the transfer gates 44 and 45 are opened again. The output timing signal clko is a signal synchronized with a clock signal externally applied to the SDRAM device.
A mask control signal dm is applied to the block 20-0. Similarly, mask control signals are respectively applied to the blocks 20-1-20-n. The mask control signal dm applied to the block 20-0 determines whether the block 20-0 should output data. When the mask control signal dm is at the high level, the transfer gates 44 and 45 output the received data signals in synchronism with the output timing signal clko. That is, the block 20-0 is set to an enabled (active) state. When the mask control signal dm is at the low level, the transfer gates 44 and 45 are continuously in the closed state and output no data signals. That is, the block 20-0 is set to a disabled (inactive) state. The mask control signal dm is generated by a control circuit, which is not shown in FIG. 1. The above control circuit receives mask data from the outside of the SDRAM device, and generates the mask block signals dm respectively supplied to the blocks 20-0-20 -n.
FIGS. 2A and 2B respectively illustrate arrangements for masking output data. By way of example, each of the arrangements includes four blocks and output circuits. The combination of four blocks and four output circuits is common to the SDRAM devices having different specifications. The arrangement shown in FIG. 2A is applied to an SDRAM device which has data output terminals 53-0-53-3 that are equal in number to the blocks 8-0-8-3 and the output circuits 20-0-20-3. In the arrangement shown in FIG. 2A, the output circuits 20-0-20-3 are respectively connected to the data output terminals 53-0-53-3. The arrangement shown in FIG. 2B is applied to an SDRAM device which has a single data output terminal 53 with regard to the blocks 8-0-8-3 and the output circuits 20-0-20-3. In the arrangement shown in FIG. 2B, blocks 1-0-1-3 are connected to only the output circuit 20-0, which is connected to the data output terminal 53. In this case, the mask control signals dm applied to the output circuits 20-1-20-3 are low, so that the output circuits 20-1-20-3 can be prevented from outputting data.
In order to arbitrarily set the data width by the mode instruction signal externally supplied, the arrangement shown in FIG. 2A is modified so that the mask control signals dm applied to the output circuits 8-0-8-3 can be controlled. When the data width is changed, the number of output circuits to be activated is changed.
However, the above-mentioned conventional memory device has the following disadvantages. The output timing signal clko is constant irrespective of the number of output circuits to be activated. However, in practice, the time it takes data to be output from the output circuits depends on the number of output circuits to be activated. This is because a drop of the power supply voltage and/or the influence of noise depend on the number of output circuits to be activated.
FIG. 3 shows changes of output data with respect to the output timing signal clko. Output data Dout is obtained when the output data width is short, and a small number of output circuits is activated. In contrast, output data Dout' is obtained when the output data width is long, and a large number of output circuits is activated. When a large number of output circuits is activated, a large power supply drop and large noise occur. Hence, the time t2 it takes the output data Dout' to be changed after the output timing signal clko rises is longer than the time t1 it takes the output data Dout to be changed after the output timing signal clko rises. When a small number of output circuits is activated, the reset time for output data is short and the data hold time is thus reduced.
As described above, the data is output at the different timings based on the number of output circuits to be activated.
Generally, the frequency of the clock is determined taking into account the dispersion of the data output timing dependent on the number of output circuits to be activated. Hence, it is very difficult to increase the clock frequency. The above disadvantages occur not only in the SDRAM devices but also in semiconductor devices in which the number of circuits to be activated is changed and the operation timings are thus changed.